1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof.
2. Description of the Related Art
Recently, Cu has been used instead of Al as wirings of semiconductor devices in order to decrease the resistance of wirings and to improve the resistance of migration such as electro migration (EM) and stress migration (SM) which becomes a cause of defective wiring.
It is hard to fabricate Cu by RIE (Reactive Ion Etching) which is used for Al. Therefore, the following damascene method is used to form wirings of Cu. Specifically, grooves and holes are formed on the surface of an insulating film, a Cu film is formed on the insulating film such that Cu is buried in the grooves and holes, and then unnecessary portions of the Cu film are removed by chemical mechanical polishing. As a result, the wirings are formed.
As a Cu film forming method according to the damascene method, an electrolytic plating method is extensively used. To a plating solution used for the electrolytic plating are mixed prescribed amounts of, for example, additives such as an accelerator, a suppressor and a leveler in addition to Cu ions in order to improve an embedding property and to realize evenness of the Cu film surface. The additives are included as impurities into the Cu film.
But, if the impurity concentration in the Cu film is high, the impurities may deposit as a result of a heat treatment to produce voids in the wirings. Here, if the voids are formed in via-plugs of an upper layer or portions immediately below contact plugs, conduction failure is caused at the via-plugs or contact plugs, possibly resulting in a failure in initial electric property.
Meanwhile, if the impurity concentration in the Cu film is low, microvoids are spread quickly because the Cu film has an uniform crystal structure, and reliability of the stress migration (SM) lowers considerably.
There is disclosed a technology that dummy patterns of an insulating material are formed in the wirings of a lower layer to surround via holes of an upper layer, thereby preventing voids from being produced in the portions immediately below the via holes (see JP-A 2004-327666 (KOKAI)).